CDA EVM9 Manuale Utente Scaricare il pdf (Pagina 38)

7

Agilent Template Tutorial

15 April, 2002

Agilent Restricted

Page 13

Triggers are generated at

the timing of CFN0, CFN3

and CFN6 from System

Simulator

UE

Ext. trigger

TX tester

(E4445A)

System Simulator

(E5515C)

SS establishes RMC12.2kbps loopback test

mode (RB test mode) after call

connection

After UE TX power adjustment sequence,

SS set up Pattern A compressed

frame

SS sends TPC commands for CFN0, 1 and 2

䇭䇭䇭䇭䇭䇭䇭䇭䇭䇭䇭SS generates

external trigger to TX tester at the

timing of CFN0

TX tester captures UL slot powers during

CFN0,1 and 2

Same measurements for CFN3, 4 and 5

Same sequence for Pattern B (CFN6, 7, 8

and 9)

Overview of test sequence

Capture time domain

uplink power triggered by

external trigger

Uplink Compressed mode Measurement

Agilent Template Tutorial

15 April, 2002

Agilent Restricted

Page 14

5.7 Power Setting in uplink compressed mode

25

µ

s

Up-Link

DPDCH

Up-Link

DPCCH

Average Power

Minimum

Power

Average Power

2

5

µs

25

µ

s

A

verage Powe

r

Slot boundaries

140

CFN 0 1 2

Tx gap

Tx gap

Slot #

CFN 6 7

Tx gap

8 9

2560 chips

UL

DPDCH

25Ps

Total

Power

Compressed Frame(s)

2560 chips 2560 chips

2560 chips

2560 chips 2560 chips

UL

DPCCH

P

a

[dB]

P

b

[dB]

P

c

[dB]

P

d

[dB]

P

e

[dB]

P

f

[dB]

25Ps25Ps

25Ps

Tx gap

P

g

[dB]

25Ps

25Ps

25Ps

25Ps

25Ps

25Ps

25Ps

25Ps

25Ps

Pattern A Test

Pattern B Test

(3)䇭䇭䇭䇭䇭䇭䇭 (4)䇭䇭䇭䇭䇭䇭 (5)

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